1. Field of the Invention
Embodiments of the invention relate to a liquid crystal display (LCD) device and a method of fabricating the liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a passivation pattern and a method of fabricating the array substrate through a three-mask process.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices use the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. The liquid crystal molecules have long, thin, shapes, and have an initial alignment direction, including initial pretilt angles. The alignment direction can be controlled by applying an electric field. Due to an optical anisotropy property of liquid crystal, the refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling the applied electric field, an image having a desired brightness can be produced.
Among the known types of liquid crystal displays (LCDs), active matrix LCDs (AM-LCDs), which have thin film transistors (TFTs) and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images. An array substrate for a liquid crystal display (LCD) device may be fabricate through a four-mask process and the fabrication method will be illustrated hereinafter.
FIG. 1 is a schematic top view showing an array substrate for a liquid crystal display device according to the related art. In FIG. 1, a gate line 20, a gate electrode 25 and a gate pad 52 are formed on a substrate 10. The gate electrode 25 extends from the gate line 20 and the gate pad 52 is formed at one end of the gate line 20. Further, a data line 30, a source electrode 32, a drain electrode 34 and a data pad 62 are formed on the substrate 10. The data line 30 crosses the gate line 20 to define a pixel region P. The source electrode 32 extends from the data line 30 and the drain electrode 34 is spaced apart from the source electrode 32. The data pad 62 is formed at one end of the data line 30. A gate pad terminal 54 on the gate pad 52 is connected to the gate pad 52 through a gate pad contact hole CH2, and a data pad terminal 64 on the data pad 62 is connected to the data pad 62 through a data pad contact hole CH3.
FIGS. 2A to 2I are schematic cross-sectional views taken along the line II-II′ of FIG. 1, showing a fabricating method of an array substrate for a liquid crystal display device using a four-mask process according to the related art.
A thin film transistor (TFT) T is connected to the gate line 20 and the data line 30. The TFT T includes the gate electrode 25, a semiconductor layer 42 (of FIG. 2I), the source electrode 32 and the drain electrode 34. The semiconductor layer 42 is formed over the gate electrode 25, and the source and drain electrodes 32 and 34 contact the semiconductor layer 42. The semiconductor layer 42 includes an active layer 40 of intrinsic amorphous silicon (a-Si:H) and an ohmic contact layer 41 (of FIG. 2I) of an impurity-doped amorphous silicon (n+ a-Si:H). In addition, the semiconductor layer 42 has the same shape as and is formed under the data line 30, the data pad 62, the source electrode 32 and the drain electrode 34. Specifically, the active layer 40 is exposed out of the data line 30, the source electrode 32 and the drain electrode 34. Moreover, the active layer 40 is exposed between the source electrode 32 and the drain electrode 34 by partially removing an ohmic contact pattern 41b (of FIG. 2F) to define a channel region ch (of FIG. 2G) for current flow.
A pixel electrode 70 is formed in the pixel region P and connected to the drain electrode 34 through a drain contact hole CH1. The pixel electrode 70 overlaps the gate line 20 corresponding to a neighboring pixel region to define a storage capacitor Cst including an overlapped portion of the gate line 20 as a first capacitor electrode and an overlapped portion of the pixel electrode 70 as a second capacitor electrode.
FIG. 2A shows a first mask process, a gate line 20, a gate electrode 25 and a gate pad 52 are formed on a substrate 10 having a pixel region P by depositing and patterning a conductive metallic material such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum (Al) alloy or chromium (Cr). Although not shown in FIG. 2A, the gate electrode 25 extends from the gate line 20 and the gate pad 52 is formed at one end of the gate line 20. A gate insulating layer 45 is formed on the gate line 20, the gate electrode 25 and the gate pad 52. The gate insulating layer 45 includes an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO2).
FIGS. 2B to 2G show a second mask process. In FIG. 2B, an intrinsic silicon layer 40a and a doped silicon layer 41a are sequentially formed on the gate insulating layer 45. The intrinsic silicon layer 40a includes intrinsic amorphous silicon (a-Si:H) and the doped silicon layer 41a includes impurity-doped amorphous silicon layer (n+ a-Si:H). For example, the intrinsic silicon layer 40a and the doped silicon layer 41a may be sequentially formed in the chamber where the gate insulating layer 45 is formed using a chemical vapor deposition (CVD) method. Next, a source drain metal layer 75 is formed on the doped silicon layer 41a. The source drain metal layer 75 includes a conductive metallic material such as copper (Cu), molybdenum (Mo), aluminum (Al), aluminum (Al) alloy or chromium (Cr).
In FIG. 2C, a photoresist (PR) layer 80 is formed on the source drain metal layer 75 and a mask HTM is disposed over the PR layer 80. The mask HTM has a transmissive area A, a half-transmissive area B and a blocking area C. Transmittance of the half-transmissive area B is smaller than transmittance of the transmissive area A and greater than transmittance of the blocking area C. The transmittance of the half-transmissive area B is obtained by forming a half-transmissive film or forming a slit pattern. Accordingly, when the PR layer is exposed to light through the mask HTM, the PR layer 80 corresponding to the half-transmissive area B is incompletely exposed. In addition, the PR layer corresponding to the transmissive area A is completely exposed and the PR layer corresponding to the blocking area C is not exposed. The blocking area C is disposed to correspond to a data line 30 (of FIG. 2E), a data pad 62, a source electrode 32 (of FIG. 2G) and a drain electrode 34 (of FIG. 2G) formed in a subsequent process, and the half-transmissive area B is disposed to correspond to a channel region ch (of FIG. 2G) between the source and drain electrodes 32 and 34 formed in a subsequent process.
FIG. 2D shows first, second and third PR patterns 82, 84 and 86 formed on the source drain metal layer 75 by exposing and developing the PR layer 80. The first PR pattern 82 has a first portion 82a corresponding to the half-transmissive area B (of FIG. 2C) and second 82b portions corresponding to the blocking area C (of FIG. 2C). Accordingly, the first portion 82a between the second 82b portions has a first thickness t82a smaller than the second thickness t82b of the second portions 82b. Further, since the second and third PR patterns 84 and 86 correspond to the blocking area C (of FIG. 2C), the second and third PR patterns 84 and 86 have the second thickness t82b. The second and third PR patterns 84 and 86 correspond to the data line 30 (of FIG. 2E) and the data pad 62 (of FIG. 2C), respectively. The PR layer 80 (of FIG. 2C) corresponding to the transmissive area A (of FIG. 2C) is completely removed to expose the source drain metal layer 75 (of FIG. 2D).
In FIG. 2E, the source drain metal layer 75 (of FIG. 2D) is patterned by using the first, second and third PR patterns 82, 84 and 86 as an etching mask to form a source drain metal pattern 72, the data line 30 and the data pad 62. The source drain metal pattern 72, the data line 30 and the data pad 62 correspond to the first, second and third PR patterns 82, 84 and 86, respectively. Further, the source drain metal layer 75 (of FIG. 2D) corresponding to the transmissive area A (of FIG. 2C) is completely removed to expose the doped silicon layer 41a. Although not shown in FIG. 2E, the source drain metal pattern 72 is electrically connected to the data line 30.
The doped silicon layer 41a (of FIG. 2D) and the intrinsic silicon layer 40a (of FIG. 2D) are patterned by using the first, second and third PR patterns 82, 84 and 86 as an etching mask to form an active layer 40 and an ohmic contact pattern 41b. As a result, the active layer 40 and the ohmic contact pattern 41b have the same shape as and are formed under the source drain metal pattern 72, the data line 30 and the data pad 62. Although the active layer 40 and the ohmic contact pattern 41b are required to have an island shape only under the source drain metal pattern 72, the active layer 40 and the ohmic contact pattern 41b are formed under the data line 30 and the data pad 62 as well as the source drain metal pattern 72. The active layer 40 and the ohmic contact pattern 41b under the data line 30 and the data pad 62 also extend from the active layer 40 and the ohmic contact pattern 41b under the source drain metal pattern 72 because the source drain metal layer 72, the doped silicon layer 41a and the intrinsic silicon layer 40a are patterned altogether.
In FIG. 2F, the first, second and third PR patterns 82, 84 and 86 have been partially removed by an ashing. As a result, the first portion 82a (FIG. 2E) of the first PR pattern 82 having the first thickness t82a is completely removed to expose the source drain metal pattern 72. In addition, the second portions 82b (FIG. 2E) of the first PR pattern 82, the second PR pattern 84 and the third PR pattern 86 having the second thickness t82b are partially removed to have a reduced thickness tr smaller than the second thickness. Since the ashing is an isotropic process, side portions of the first, second and third PR patterns 82, 84 and 86 are also removed to expose first edge portions F at outer edges of the source drain metal pattern 72, the data line 30 and the data pad 62. Further, second edge portions G (of FIG. 2E) inside the source drain metal pattern 72 are also exposed.
In FIG. 2G, the source drain metal pattern 72 and the ohmic contact pattern 41b have been patterned by using the partially removed first, second and third PR patterns 82. 84 and 86 to form a source electrode 32, a drain electrode 34 and an ohmic contact layer 41. The active layer 40 and the ohmic contact layer 41 are defined as a semiconductor layer 42, and the gate electrode 25, the semiconductor layer 42, the source electrode 32 and the drain electrode 34 define a thin film transistor (TFT) T. The active layer 40 exposed between the source and drain electrodes 32 and 34 is used as a channel region ch. Since the ohmic contact pattern 41b in the first edge portions F is eliminated, the active layer 40 in the first edge portions F is protruded beyond the outer edges of the data line 30, the data pad 62, the source electrode 32 and the drain electrode 34. In addition, since the ohmic contact pattern 41b in the second edge portions G is eliminated, the channel region ch of the active layer 40 has a length greater than a designed value. This may cause deterioration of the TFT T. Next, the first, second and third PR patterns 82, 84 and 86 are removed by a stripping.
FIG. 2H shows a third mask process. In FIG. 2H, a passivation layer 55 is formed on the data line 30 and the TFT T by depositing and patterning one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO2) and an organic insulating material such as benzocyclobutene (BCB) and acrylic resin. The passivation layer 55 has a drain contact hole CH1 exposing the drain electrode 34, a gate pad contact hole CH2 exposing the gate pad 52 and a data pad contact hole CH3 exposing the data pad 62. The gate pad contact hole CH2 is formed in the gate insulating layer 45 and the passivation layer 55, while the drain contact hole CH1 and the data pad contact hole CH3 are formed in the passivation layer 55. Accordingly, the gate pad 52 may be incompletely exposed, or the drain electrode 34 and the data pad 62 may have etch damage due to the length of exposure. The incomplete exposure and the damage may cause deterioration in contact property.
FIG. 2I shows a fourth mask process. In FIG. 2I, a pixel electrode 70, a gate pad terminal 54 and a data pad terminal 64 are formed on the passivation layer 55 by depositing and patterning a transparent conductive material such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). The pixel electrode 70 is connected to the drain electrode 34 through the drain contact hole CH1. In addition, the gate pad terminal 54 is connected to the gate pad 52 through the gate pad contact hole CH2 and the data pad terminal 64 is connected to the data pad 62 through the data pad contact hole CH3. The pixel electrode 70 overlaps the gate line 20 corresponding to a neighboring pixel region to define a storage capacitor Cst having overlapped portions of the gate line 20 and the pixel electrode 70 as first and second capacitor electrodes, respectively, and the gate insulating layer 45 and the passivation layer 55 as a dielectric layer.
In the array substrate for an LCD device fabricated through a four-mask process according to the related art, since the data line 30, the source electrode 32, the drain electrode 34 and the semiconductor layer 42 are formed again using the same mask (the second mask), the semiconductor layer 42 is formed under the data line 30, the source electrode 32 and the drain electrode 34. Specifically, since the active layer 40 under the source electrode 32 is connected to the active layer 40 under the data line 30, the active layer 40 of the TFT T is protruded beyond the gate electrode 25. As a result, a photocurrent is generated in the protruded portion of the active layer 40 of the TFT T due to exposure to a backlight unit and causes deterioration in the electrical properties of the TFT T.
In addition, the active layer 40 under the data line 30 is protruded beyond the outer edges of the data line 30. The photocurrent may be generated in the protruded portion of the active layer 40 under the data line 30. Further, since the active layer 40 under the data line 30 is closer to the pixel electrode 70 than the data line 30, a coupling capacitance between the active layer 40 under the data line 30 and the pixel electrode 70 is greater than a coupling capacitance between the data line 40 and the pixel electrode 70. The increased coupling capacitance between the active layer 40 under the data line 30 and the pixel electrode 70 causes a wavy noise that ripple patterns are displayed.